1. Field of the Invention
The present invention relates generally to a method of fabricating a scaled non-volatile semiconductor memory device and, more particularly, to methods of fabricating a stack-gate non-volatile semiconductor memory device having a tapered floating-gate structure and its contactless memory arrays for high-density mass storage applications.
2. Description of Related Art
A non-volatile semiconductor memory device is known to store charges in an isolated gate being known as a floating gate by means of either Fowler-Nordheim tunneling or hot-electron injection through a thin tunneling-dielectric layer from a semiconductor substrate for programming and to remove or erase charges stored in the isolated gate by means of Fowler-Nordheim tunneling through a thin tunneling-dielectric layer to the source diffusion region of a semiconductor substrate or a control gate. Basically, the cell size of a non-volatile semiconductor memory device must be scaled down for high-density mass storage applications and the cell structure must be developed toward low-voltage, low-current and high-speed operation with high endurance and high retention.
In general, the non-volatile semiconductor memory devices of the prior arts can be divided into two categories, based on the cell structure: a stack-gate structure and a split-gate structure. The stack-gate structure is known to be a one-transistor cell, in which the gate length of a cell can be defined by using a minimum-feature-size (F) of technology used. However, the split-gate structure including a floating gate and a select gate is known to be a 1.5-transistor cell. Therefore, the stack-gate structure is more suitable for high-density mass storage applications than the split-gate structure.
FIG. 1A shows a cross-sectional view of a stack-gate non-volatile semiconductor memory device in the channel-length direction, in which a thin tunneling-oxide layer 101 is formed over a semiconductor substrate 100; a doped polycrystalline-silicon layer 102 being acted as a floating gate is formed over the thin tunneling-oxide layer 101; an intergate-dielectric layer 103 of preferably an oxide-nitride-oxide (ONO) structure is formed on the floating gate 102; a doped polycrystalline-silicon layer 104 capped with a silicide layer either using polycide or salicide technology is formed over the intergate-dielectric layer 103 to act as a control gate; a source diffusion region is formed with a double-diffused structure having a shallow heavily-doped diffusion region 106a formed within a deeper moderately-doped diffusion region 105a; a drain diffusion region 106b is formed by a shallow heavily-doped diffusion region in the semiconductor substrate 100; and a pair of sidewall dielectric spacers 106 are formed over sidewalls of a gate stack.
Basically, the operation principle of a stack-gate non-volatile semiconductor memory device shown in FIG. 1A had been described by Mukherjee et al. in U.S. Pat. No. 4,698,787. The programming of a stack-gate non-volatile semiconductor memory device shown in FIG. 1A can be accomplished by applying a relatively high positive-voltage to a control gate 104, a moderately high positive-voltage to a drain 106b, and a source 106a is grounded. A high lateral electric field near the drain edge is used to generate hot-electrons and the generated hot-electrons with an energy higher than the interface barrier between the conduction bands of a thin tunneling-oxide layer 101 and the semiconductor substrate 100 are injected into a floating gate 102 and stored there. The erasing of the stack-gate non-volatile semiconductor memory device shown in FIG. 1A can be accomplished by applying a relatively high negative-voltage to the control gate 104 and a moderately high positive-voltage to the source 106a, and the drain 106b is usually kept floating. The stored electrons in the floating gate 102 are then tunneling from the floating gate 102 to the double-diffused source structure 106a, 105a by a high electric field across the thin tunneling-oxide layer 101 over the double-diffused source structure. The double-diffused source structure is mainly used to eliminate the band-to-band tunneling effects during erasing and a deeper double-diffused source junction is therefore needed to have a large overlapping area for a thin tunneling-oxide layer in order to increase the erasing speed.
Apparently, as the gate length of a stack-gate non-volatile semiconductor memory device shown in FIG. 1A is scaled for high-density mass storage applications, there is an important issue encountered: the deeper double-diffused source structure becomes an obstacle for a scaled stack-gate length because the punch-through effect becomes serious for programming using hot-election injection as stated above. It is, therefore, an objective of the present invention to provide a non-volatile semiconductor memory device having a tapered floating-gate structure and its fabrication method for a scaled stack-gate length to alleviate the problems encountered by the prior arts.
As the stack-gate non-volatile semiconductor memory device shown in FIG. 1A is implemented as a cell of a memory array, for example: a NOR-type memory array, the source of the stack-gate non-volatile semiconductor memory devices in a column are connected each other by a common-source line (SL) and the nearby two columns use the same common-source line (SL). The common-source line (SL) for nearby two columns is in general implemented by first completely removing the field-oxides in the field-oxide isolation regions using a non-critical masking step and then implanting doping impurities into a semiconductor substrate to form a buried common-source line. FIG. 1B shows a cross-sectional view along a buried common-source line for LOCOS isolation. It is clearly shown that a non-uniform doping depth 106c, 106d would occur over the side-slope formed by LOCOS, resulting in higher buried common-source line resistance. This phenomenon would be more serious for shallow-trench-isolation (STI) when compared to LOCOS isolation, as shown in FIG. 1C.
There are several methods proposed to improve the buried common-source line resistance. U.S. Pat. No. 6,211,020 B1 had proposed a plasma implantation technique to improve the non-uniform doping depth resulting from conventional ion-implantation. However, the buried common-source line resistance is still high because the junction depth of a plasma implantation will be limited by the source junction depth of a scaled non-volatile semiconductor memory device. Moreover, a large junction capacitance of the buried common-source line together with a high parasitic resistance of the buried common-source line may reduce the operation speed of a non-volatile semiconductor memory array for high-density mass storage applications. U.S. Pat. No. 6,221,718 B1 had proposed the parallel common bit-lines for the source/drain diffusion regions of all cells using a doped polycrystalline-silicon layer. The doped polycrystalline-silicon layer must be thinner than the thickness of the floating gate in order to run an intergate ONO layer and a control gate. It is clearly seen from the formed structure that a very high parasitic capacitance between the control gate and the common bit-lines is expected. U.S. Pat. No. 6,211,012 B1 had described a conductive layer including tungsten, aluminum or doped polycrystalline-silicon as the common-source lines and the landing pads for the bit-line contacts. A planarized CVD-oxide layer and a critical alignment mask step are required to pattern the landing pads. Moreover, a critical mask is also required to register the stack-gate over the pre-isolated substrate shown. It is, therefore, another objective of the present invention to provide a contactless structure with the common-source/drain conductive bus lines having very low common bus-line resistance and capacitance, and the highly conductive landing islands for the scaled stack-gate non-volatile semiconductor memory arrays in high-density mass storage applications.
A stack-gate non-volatile memory device and its contactless memory arrays are disclosed by the present invention. The stack-gate non-volatile memory device of the present invention comprises a stack-gate structure having a tapered floating-gate layer being formed over a first gate-dielectric layer; a first sidewall dielectric layer being formed over each sidewall of the tapered floating-gate layer, a second sidewall dielectric layer being formed over each sidewall of a control-gate layer, and a second gate-dielectric layer being formed over a semiconductor substrate in each side portion of the stack-gate structure; a source diffusion region and a drain diffusion region being separately or simultaneously formed in a self-aligned manner by implanting doping impurities across the tapered floating-gate structure with or without the first sidewall dielectric layers and the second gate-dielectric layers to form the graded doping profiles in the semiconductor substrate; a sidewall conductive electrode capped with a dielectric layer being formed over each of the first sidewall dielectric layers and on the second gate-dielectric layers; and a first sidewall dielectric spacer being formed over each sidewall of the stack-gate structure and on the first dielectric layers to define the sidewall conductive electrodes and the source/drain contact regions. The stack-gate non-volatile memory device as described is used to implement three contactless memory arrays: a contactless NOR-type memory array, a contactless NAND-type memory array, and a contactless parallel common-source/drain conductive bit-lines memory array.
The contactless NOR-type memory array of the present invention comprises a plurality of active regions and a plurality of shallow-trench-isolation (STI) regions being alternately formed on a semiconductor substrate of a first conductivity type; a plurality of stack-gate non-volatile memory devices being formed on the semiconductor substrate, wherein a plurality of elongated control-gate layers being formed transversely to the plurality of STI regions are acted as a plurality of word lines; a plurality of common-source conductive bus lines being formed over a plurality of first flat beds, wherein each of the plurality of first flat beds being formed between a pair of first sidewall dielectric spacers is alternately formed by an etched first raised field-oxide layer and a heavily-doped source diffusion region of a second conductivity type formed within a common-source diffusion region of the second conductivity type and each of the plurality of common-source conductive bus lines is integrated with the source-sidewall conductive electrodes of nearby stack-gate non-volatile memory devices; a plurality of planarized common-drain conductive islands being formed over a plurality of second flat beds, wherein each of the plurality of second flat beds being formed between another pair of first sidewall dielectric spacers and alternately formed by an etched first raised field-oxide layer and a heavily-doped drain diffusion region of the second conductivity type formed within a common-drain diffusion region of the first or second conductivity type, and each of the plurality of planarized common-drain conductive islands is integrated with a pair of drain-sidewall conductive electrodes of nearby stack-gate non-volatile memory devices; and a plurality of bit lines integrated with the plurality of planarized common-drain conductive islands being formed alternately and transversely to the plurality of common-source conductive bus lines, wherein each of the plurality of bit lines together with the plurality of planarized common-drain conductive islands in a column are simultaneously patterned and etched by a masking dielectric layer being aligned to each of the plurality of active regions and two sidewall dielectric spacers being formed over each sidewall of the masking dielectric layer.
The contactless NAND-type memory array of the present invention comprises a plurality of active regions and a plurality of STI regions being alternately formed on a semiconductor substrate of a first conductivity type; a plurality of stack-gate non-volatile memory devices being formed on the semiconductor substrate, wherein a plurality of elongated control-gate conductive layers being formed transversely to the plurality of STI regions are acted as a plurality of word lines; a plurality of self-registered common-source conductive islands being formed on a plurality of heavily-doped source diffusion regions of a second conductivity type formed within a plurality of common-source diffusion regions of the second conductivity type, wherein each of the plurality of self-registered common-source conductive islands being formed between a pair of first sidewall dielectric spacers and nearby second raised field-oxide layers is integrated with the source-sidewall conductive electrodes of nearby stack-gate non-volatile memory devices; a plurality of self-registered common-drain conductive islands being formed on a plurality of heavily-doped drain diffusion regions of the second conductivity type formed within a plurality of common-drain diffusion regions of the second conductivity type, wherein each of the plurality of self-registered common-drain conductive islands being formed between another pair of first sidewall dielectric spacers and nearby second raised field-oxide layers is integrated with the drain-sidewall conductive electrodes of nearby stack-gate non-volatile memory devices; and a plurality of bit lines being formed alternately and transversely to the plurality of word lines, wherein each of the plurality of bit lines is patterned and etched by a masking dielectric layer being aligned to each of the plurality of active regions and two sidewall dielectric spacers being formed over each sidewall of the masking dielectric layer.
The contactless parallel common-source/drain conductive bit-lines memory array of the present invention comprises a plurality of active regions and a plurality of STI regions being alternately formed on a semiconductor substrate of a first conductivity type; a plurality of stack-gate non-volatile memory devices being formed on the semiconductor substrate; a plurality of common-source conductive bus lines being formed over a plurality of first flat beds, wherein each of the plurality of first flat beds being formed between a pair of first sidewall dielectric spacers is alternately formed by an etched first raised field-oxide layer and a heavily-doped source diffusion region of a second conductivity type formed within a common-source diffusion region of the second conductivity type and each of the plurality of common-source conductive bus lines is integrated with the source-sidewall conductive electrodes of nearby stack-gate non-volatile memory devices; a plurality of common-drain conductive bus lines being formed over a plurality of second flat beds, wherein each of the plurality of second flat beds being formed between another pair of first sidewall dielectric spacers is alternately formed by an etched first raised field-oxide layer and a heavily-doped drain diffusion region of the second conductivity type formed within a common-drain diffusion region of the first conductivity type and each of the plurality of common-drain conductive bus lines is integrated with the drain-sidewall conductive electrodes of nearby stack-gate non-volatile memory devices; and a plurality of word lines being formed transversely to the plurality of common-source/drain conductive bus lines, wherein each of the plurality of word lines being integrated with a plurality of control-gate conductive islands is simultaneously patterned and etched by a masking dielectric layer being aligned to each of the plurality of active regions and two sidewall dielectric spacers being formed over each sidewall of the masking dielectric layer.